Amplifier Architecture & Topology Engineering
We design custom microwave amplifier circuits tailored to your exact frequency band, thermal constraints, and linearity standards. Every topology is optimized using non-linear foundry PDK models.
GaN High-Power Amplifiers (HPAs)
High power density microwave power amplifiers fabricated on GaN-on-SiC substrates (Wolfspeed, Qorvo, NXP). Optimized in Class AB, Class F, and Inverse-F topologies utilizing harmonic load-pull contours to balance peak output power, breakdown limits, and maximum drain efficiency.
Sub-1 dB Ultra-Low-Noise Amplifiers (LNAs)
Receiver front-end LNAs synthesized for minimum noise measure (F_min) while simultaneously achieving low input VSWR (< 1.25:1). Includes inductive source degeneration, out-of-band resistive loading, and rigorous Rollett stability verification across all operating temperatures.
Doherty & Envelope-Tracking PAs
Symmetrical and asymmetrical Doherty architectures featuring main (carrier) and peaking stages with dynamic quarter-wave impedance inverters. Maintains exceptional drain efficiency under modern high Peak-to-Average Power Ratio (PAPR) 5G NR and wideband satellite signals.
Balanced & Distributed Amplifiers
Multi-octave distributed synthetic transmission-line amplifiers and quadrature balanced amplifiers using 90° branchline or Lange couplers. Delivers low VSWR, flat group delay, and resilience against load mismatches without external isolators.
DC Biasing Networks & Safe Power Sequencing
Biasing high-power GaN and GaAs devices demands far more than a simple resistor divider. Improper turn-on order triggers immediate gate-lag or catastrophic thermal runaway, while poor decoupling introduces electrical memory effects.
Negative gate voltage must be fully stabilized before positive drain voltage is enabled. Reverse shutdown prevents inductive drain latch-up.
Hardware-Enforced Gate Sequencing
Discrete or PMIC-driven sequential control. Dedicated charge pumps generate negative gate rails (-5V to -2V) with strict "power-good" analog comparator flags before triggering high-side PMOS/NMOS drain switches.
Temperature-Compensated IDQ
GaN and LDMOS threshold voltages drift with channel temperature (T_j), causing transconductance shift and intermodulation asymmetry. We synthesize active bias controllers with analog linear temperature coefficients:
High Video Bandwidth (VBW) Decoupling
Wideband 5G NR and pulsed radar signals generate envelope modulation frequencies. High drain feed impedance at envelope frequencies induces electrical memory effects, causing severe 2-tone IMD asymmetry.
Electromagnetic & Circuit Co-Simulation Pipeline
Ideal schematic simulations fail to predict microwave reality because bond wires, copper surface roughness, via inductances, and package cavity resonances shift impedances by 20% to 40%. Our co-simulation workflow eliminates physical cut-and-try.
Active Device Synthesis
Import foundry non-linear large-signal PDK models (Angelov, ASM-HEMT, or EEsof Root models). Perform DC IV sweeps and evaluate intrinsic Rollett stability criteria.
Fundamental & Harmonic Load-Pull
Synthesize optimum source and load impedance loci across 2f₀ and 3f₀ harmonics. Map constant output power and PAE contours on the Smith chart to identify trade-offs.
3D FEM Layout Extraction
Model physical matching networks, bond wire profiles, ground via fences, and dielectric layers in Ansys HFSS. Extract true multi-port N-port scattering matrices.
Harmonic Balance Verification
Re-connect active transistor models directly to the full-wave 3D electromagnetic S-parameter block. Run harmonic balance to verify gain, 1-dB compression, and stability.
Signal & Power Integrity (SI / PI) Verification
High-frequency power amplifiers demand rigorous co-verification between the RF signal path and the DC power distribution network. Voltage sag on drain rails corrupts modulation constellations and causes spectral regrowth.
Power Distribution Network (PI)
Ansys SIwave • Keysight PIProWe analyze power plane impedance from DC to 1 GHz. Voltage drop simulations ensure maximum 15 mV DC IR drop along heavy copper traces, preventing thermal hotspots under 10A+ pulsed peak currents.
Modulated Linearity (SI)
Keysight Virtual TestbenchesWe verify modulated system metrics using 5G NR, QAM-256, and wideband radar waveforms. Non-linear distortions (AM-AM gain compression and AM-PM phase conversion) are minimized to satisfy spectral masks.
Complete Engineering Deliverables Package
Every amplifier contract delivers full intellectual property and uncompiled engineering assets for immediate CAD and fab handoff.
Native Solver Archives
Uncompiled Keysight ADS .wrk workspaces and Ansys HFSS .aedt 3D parametric models.
De-Embedded S-Parameters
Multi-port .s2p and .s4p Touchstone files referenced to 50 Ω planes with noise parameters (F_min, Rn).
Fabrication Layout Data
Gerber RS-274X, ODB++, and IPC-2581 files with copper thickness, via-fence stitching, and thermal relief rules.
Verification Report
Detailed PDF including load-pull contours, AM-AM/AM-PM graphs, EVM measurements, and thermal dissipation maps.